Update hw acceleration authored by Ladislav Lhotka's avatar Ladislav Lhotka
# Hardware-Accelerated DNS Monitoring Platform # Hardware-Accelerated DNS Monitoring Platform
The aim of this project is to develop a hardware-accelerated DNS collector capable of processing DNS traffic at 10 Gbps wire speed. The aim of this project is to develop a hardware-accelerated DNS collector capable of processing DNS traffic at 10 Gbps wire speed using a programmable hardware card that was developed independently at the Faculty of Information Technology, VUT Brno. This card combines a field-programmable gate array (FPGA) with a high-performance network processor (NXP).
## Hardware Setup ## Hardware Setup
...@@ -8,11 +8,8 @@ The following diagram shows a typical deployment in which hardware-accelerated m ...@@ -8,11 +8,8 @@ The following diagram shows a typical deployment in which hardware-accelerated m
![schema](img/hw.png) ![schema](img/hw.png)
The host machine has two cards connected to Express PCI: The host machine has two cards connected to Express PCI, namely the FPGA/NXP card and a
standard two-port 10GE card (Intel).
* a programmable hardware card with an FPGA chip and a network processor (NXP)
* standard two-port 10GE card (Intel).
The FPGA/NXP card has three 10GE interfaces: one external (denoted as E), and two internal (A and B). The FPGA/NXP card has three 10GE interfaces: one external (denoted as E), and two internal (A and B).
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