- 29 Jan, 2019 3 commits
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Marek Behun authoredThis is a bugfix for Turris Mox, do not send to mainline. Signed-off-by:
Marek Behún <marek.behun@nic.cz> -
Marek Behun authored
This adds basic support for the Turris Mox board from CZ.NIC. Turris Mox is a modular router based on the Armada 3720 SOC (same as EspressoBin). The basic module can be extended by different modules. When those modules are connected, U-Boot shall patch this basic device-tree with nodes corresponding to those modules. Signed-off-by:Marek Behún <marek.behun@nic.cz> -
Marek Behun authored
This adds a driver to communicate with the firmware running on the secure processor of the Turris Mox router, enabling the kernel to retrieve true random numbers from the Entropy Bit Generator and to sign messages with the ECDSA private key burned into each Turris Mox device. This also adds support to read the device serial number and other manufacturing information. Signed-off-by:Marek Behún <marek.behun@nic.cz>
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- 12 Dec, 2018 37 commits
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Marek Behun authored
This adds node for the rWTM mailbox. rWTM is a Cortex-M3 processor on the Armada 37xx SOC used for security purposes. Signed-off-by:Marek Behún <marek.behun@nic.cz> -
Marek Behun authored
This adds support for the mailbox via which the kernel can communicate with the firmware running on the secure processor of the Armada 37xx SOC. The rWTM secure processor has access to internal eFuses and cryptographic circuits, such as the Entropy Bit Generator to generate true random numbers. Signed-off-by:Marek Behún <marek.behun@nic.cz> -
Marek Behun authored
Add code to do a warm reset on the PHY and PCIE cores and if PERSTN GPIO is specified in device tree (as reset-gpio), also reset the card. Signed-off-by:Marek Behún <marek.behun@nic.cz> -
Marek Behun authored
This adds the system controller node for CPU Miscellaneous Registers (which is needed for the watchdog node) and the watchdog node. Signed-off-by:Marek Behún <marek.behun@nic.cz> -
Marek Behun authored
Add documentation for the kernel module parameters accepted by armada-37xx-wdt. Signed-off-by:
Marek Behún <marek.behun@nic.cz>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
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Marek Behun authored
This adds device tree binding documentation for the CPU watchdog found on Armada 37xx SOCs (EspressoBin, Turris Mox). Signed-off-by:Marek Behún <marek.behun@nic.cz>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org -
Marek Behun authored
This adds support for the CPU watchdog found on Marvell Armada 37xx SoCs. There are 4 counters which can be set as CPU watchdog counters. This driver uses the second counter (ID 1, counting from 0) as watchdog counter, and first counter (ID 0) to implement pinging on the second counter without the need to disable it. Since counters IDs 2 and 3 are enabled already before even U-Boot starts, this driver does not use them at all, for example by adding a device tree property for counter selection. Signed-off-by:
Marek Behún <marek.behun@nic.cz>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Marek Behun authored
This adds support for interpreting the input and output bits of one device on Moxtet bus as GPIOs. This is needed for example by the SFP cage module of Turris Mox. Signed-off-by:Marek Behun <marek.behun@nic.cz> -
Marek Behun authored
On the Turris Mox router there can be connected different modules to the main CPU board, currently a module with a SFP cage, a module with MiniPCIe connector, a 4-port switch module and a 8-port switch module, for example: [CPU]-[PCIe]-[8-port switch]-[8-port switch]-[SFP] Each of this modules has an input and output shift register, and these are connected via SPI to CPU board. Via this SPI connection we are able to discover which modules are connected and we can also read/write some configuration to the modules. Fromi/to each module 8 bits can be read (of which lower 4 bits identify the module) and written. For example from the module with a SFP cage we can read the LOS, TX-FAULT and MOD-DEF0 signals, while we can write TX-DISABLE and RATE-SELECT signals. Other modules may support something else. This driver creates a new bus type, called "moxtet". For each Mox module it finds via SPI, it creates a new device on the moxtet bus so that drivers can be written for them, for example a gpio driver for the module with a SFP cage. The topology of how Mox modules are connected can then be read by listing /sys/bus/moxtet/devices. Signed-off-by:Marek Behun <marek.behun@nic.cz> -
This allows to reference these gpio controller as interrupt parent. Also add a comment which cpu line names are managed by the controllers because "nb" and "sb" usually doesn't appear in schematics, but MPPX_Y do. Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
Gregory CLEMENT <gregory.clement@bootlin.com>
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This patch icorrects below mpp definitions: - The sdio_sb group is composed of 6 pins and not 5; - The rgmii group contains pins mpp2[17:6] and not mpp2[19:6]; - Pin of group "pmic0" is mpp1[6] but not mpp1[16]; - Pin of group "pmic1" is mpp1[7] but not mpp1[17]; - A new group "smi" is added in A0 with 2 pins - mpp2[19:18], its bitmask is bit4; - Group "pcie1" has 3 pins in A0 - mpp2[5:3], its bit mask is bit5 | bit9 | bit10 but not bit4; - Group "ptp" has 3 pins in A0 as Z1, but its bitmask is changed to bit11 | bit12 | bit13. Reviewed-on: http://vgitil04.il.marvell.com:8080/41830 Reviewed-on: http://vgitil04.il.marvell.com:8080/42774 Reviewed-on: http://vgitil04.il.marvell.com:8080/41970 Reviewed-on: http://vgitil04.il.marvell.com:8080/42775 Reviewed-by:
Wilson Ding <dingwei@marvell.com> Reviewed-by:
Evan Wang <xswang@marvell.com> Reviewed-by:
Victor Gu <xigu@marvell.com> Tested-by:
iSoC Platform CI <ykjenk@marvell.com> Tested-by:
Ken Ma <make@marvell.com> Signed-off-by:
Marek Behun <marek.behun@nic.cz> -
The mvneta Ethernet driver is used on a few different Marvell SoCs. Some SoCs have per cpu interrupts for Ethernet events, the driver uses a per CPU napi structure for this case. Some SoCs such as armada 3700 have a single interrupt for Ethernet events, the driver uses a global napi structure for this case. Current mvneta_config_rss() always operates the per cpu napi structure. Fix it by operating a global napi for "single interrupt" case, and per cpu napi structure for remaining cases. Signed-off-by:
Jisheng Zhang <Jisheng.Zhang@synaptics.com> Fixes: 2636ac3c ("net: mvneta: Add network support for Armada 3700 SoC") Reviewed-by:
David S. Miller <davem@davemloft.net>
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The mvneta Ethernet driver is used on a few different Marvell SoCs. Some SoCs have per cpu interrupts for Ethernet events. Some SoCs have a single interrupt, independent of the CPU. The driver handles this by having a per CPU napi structure when there are per CPU interrupts, and a global napi structure when there is a single interrupt. When the napi core calls mvneta_poll(), it passes the napi instance. This was not being propagated through the call chain, and instead the per-cpu napi instance was passed to napi_gro_receive() call. This breaks when there is a single global napi instance. Signed-off-by:
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Marek Behun authored
The port_set_speed method for the Topaz family must not be the same as for Peridot family, since on Topaz port 5 is the SERDES port and can be set to 2500mbps spped mode. This patch adds a new method for the Topaz family, allowing the alt_bit mode only for port 0 and 2500 mbps mode for port 5. Signed-off-by:Marek Behún <marek.behun@nic.cz> -
Marek Behun authored
On some boards the interrupt can be shared between multiple devices. For example on Turris Mox the interrupt is shared between all switches. Signed-off-by:Marek Behun <marek.behun@nic.cz> -
free_irq() waits until all handlers for this IRQ have completed. As the relevant handler (mv88e6xxx_g1_irq_thread_fn()) takes the chip's reg_lock it might never return if the thread calling free_irq() holds this lock. For the same reason kthread_cancel_delayed_work_sync() in the polling case must not hold this lock. Also first free the irq (or stop the worker respectively) such that mv88e6xxx_g1_irq_thread_work() isn't called any more before the irq mappings are dropped in mv88e6xxx_g1_irq_free_common() to prevent the worker thread to call handle_nested_irq(0) which results in a NULL-pointer exception. Signed-off-by:
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Handle polled interrupts correctly when loading the module. Signed-off-by:
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When free'ing the polled IRQs, call the common irq free code. Otherwise the interrupts are left registered, and when we come to load the driver a second time, we get an Opps. Signed-off-by:
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By calling request_threaded_irq() with the flag IRQF_TRIGGER_FALLING we override the trigger mode provided in device tree. And the interrupt is actually active low, which is what all the current device tree descriptions use. Suggested-by:
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Call the common irq free function, rather than going recursive and blowing away the stack, followed by the machine. Fixes: 294d711e ("net: dsa: mv88e6xxx: Poll when no interrupt defined") Signed-off-by:
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This changes the respective line in /proc/interrupts from 49: x x mv88e6xxx-g1 7 Edge mv88e6xxx-g1 to 49: x x mv88e6xxx-g1 7 Edge mv88e6xxx-g2 which makes more sense. Reviewed-by:
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Most of the mv88e6xxx switches have the PHYs at address 0, 1, 2, ... The 6341 however has the PHYs at 0x10, 0x11, 0x12. Add a parameter to the info structure for this base address. Testing of 6f88284f ("net: dsa: mv88e6xxx: Add MDIO interrupts for internal PHYs") was performed on the 6341. So it works only on the 6341. Use this base information to correctly set the interrupt. Fixes: 6f88284f ("net: dsa: mv88e6xxx: Add MDIO interrupts for internal PHYs") Signed-off-by:
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When registering an MDIO bus, it is possible to pass an array of interrupts, one per address on the bus. phylib will then associate the interrupt to the PHY device, if no other interrupt is provided. Some of the global2 interrupts are PHY interrupts. Place them into the MDIO bus structure. Signed-off-by:
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Add to the info structure the number of internal PHYs, if they generate interrupts. Some of the older generations of switches have internal PHYs, but no interrupt registers. In this case, set the count to zero. Signed-off-by:
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With the recent change to polling for interrupts, it is important that the number of global 1 interrupts is listed. Without it, the driver requests an interrupt domain for zero interrupts, which returns EINVAL, and the probe fails. Add two missing entries. Signed-off-by:
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Not all boards have the interrupt output from the switch connected to a GPIO line. In such cases, phylib has to poll the internal PHYs, rather than receive an interrupt when there is a change in the link state. phylib polls once per second, and per PHY reads around 4 words. With a switch typically having 4 internal PHYs, this means 16 MDIO transactions per second. Rather than performing this phylib level polling, have the driver poll the interrupt status register. If the status register indicates an interrupt condition processing of interrupts in the same way as if a GPIO was used. Polling 10 times a second places less load on the MDIO bus. But rather than taking on average 0.5s to detect a link change, it takes less than 0.05s. Additionally, other interrupts, such as the watchdog, ATU and VTU violations will be reported. Signed-off-by:
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When a port changes CMODE, the SERDES interface being used can change. Disable interrupts for the old SERDES interface, and enable interrupts on the new. Signed-off-by: -
phylink wants to know when the MAC layers notices a change in the link. For the 6390 family, this is a change in the SERDES state. Add interrupt support for the SERDES interface used to implement SGMII/1000Base-X/2500Base-X. This is currently limited to ports 9 and 10. Support for the 10G SERDES and other ports will be added later, building on this basic framework. Signed-off-by: -
An up coming change will register interrupts for individual switch ports, using the mv88e6xxx_port as the interrupt context information. Add members to the mv88e6xxx_port structure so we can link it back to the mv88e6xxx_chip member the port belongs to and the port number of the port. Signed-off-by: -
The 6390 family has a number of SERDES interfaces per port. When the cmode changes, eg 1000Base-X to XAUI, the SERDES interface in use will also change. Power down the old SERDES interface and power up the new SERDES interface. Signed-off-by: -
The ports CMODE indicates the type of link between the MAC and the PHY. It is used often in the SERDES code. Rather than read it each time, cache its value. Signed-off-by: -
The 6390 has three different SERDES interface types. 2500Base-X is implemented by the SGMII/1000Base-X SERDES. So power on/off the correct SERDES. Signed-off-by: -
Add a helper for accessing SERDES registers of the 6390 family. Signed-off-by: -
There is a need to add more functions manipulating the SERDES interfaces. Cleanup the namespace. Signed-off-by: -
Marek Behun authored
The 88E6141/6341 switches (also known as Topaz) have 1 SGMII lane, which can be configured the same way as the SERDES lane on 88E6390. Signed-off-by:Marek Behun <marek.behun@nic.cz> -
The 6390 has two SERDES interfaces, used by ports 9 and 10. The 6390X has eight SERDES interfaces. These allow ports 9 and 10 to do 10G. Or if lower speeds are used, some of the SERDES interfaces can be used by ports 2-8 for 1000Base-X. Signed-off-by: -
The 6390 family has 8 SERDES lanes. What ports use these lanes depends on how ports 9 and 10 are configured. If 9 and 10 does not make use of a line, one of the lower ports can use it. Add a function to return the lane a port is using, if any, and simplify the code to power up/down the lane. Signed-off-by:
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