Commit fb5e4368 authored by Marek Behun's avatar Marek Behun
Browse files

wtmi: uart: fix UART baudrate divisor calculation



The UART code uses the xtal clock as parent for UART baudrate
generation, but it assumes that xtal runs at 25 MHz, which isn't
necessarily the case for all A3720 boards.

Use get_ref_clk() to determine xtal clock rate.

Use rounding division to compute the divisor value.
Signed-off-by: Marek Behun's avatarMarek Behún <marek.behun@nic.cz>
Suggested-by: default avatarPali Rohár <pali@kernel.org>
parent b8928b29
......@@ -47,4 +47,9 @@ typedef u32 size_t;
#define maybe_unused __attribute__((unused))
static inline u32 div_round_closest_u32(u32 x, u32 d)
{
return (x + d / 2) / d;
}
#endif /* __TYPES_H */
......@@ -40,8 +40,6 @@
#include "stdio.h"
#include "debug.h"
#define UART_CLOCK_FREQ 25804800
const struct uart_info uart1_info = {
.rx = 0xc0012000,
.tx = 0xc0012004,
......@@ -76,8 +74,11 @@ void uart_set_stdio(const struct uart_info *info)
void uart_reset(const struct uart_info *info, unsigned int baudrate)
{
u32 parent_rate = get_ref_clk() * 1000000;
/* set baudrate */
writel((UART_CLOCK_FREQ / baudrate / 16), info->baud);
writel(div_round_closest_u32(parent_rate, baudrate * 16), info->baud);
/* set Programmable Oversampling Stack to 0, UART defaults to 16X scheme */
writel(0, info->possr);
......
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