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Verified Commit 9ba1fd13 authored by Michal Hrusecky's avatar Michal Hrusecky :mouse:
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mox patches: Fix conflict

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patches/openwrt/wip/0001-mvebu-Basic-MoX-support.patch
+ 22
− 47
View file @ 9ba1fd13
From 24740fef9f7b62992c155fd77663f9cf17e2ef95 Mon Sep 17 00:00:00 2001
From 534426512d3f7ba0720e48628701f9082edbe9b2 Mon Sep 17 00:00:00 2001
From: Michal Hrusecky <Michal@Hrusecky.net>
Date: Wed, 7 Mar 2018 17:10:32 +0100
Subject: [PATCH] mvebu: Basic MoX support
......@@ -130,10 +130,10 @@ Signed-off-by: Michal Hrusecky <Michal@Hrusecky.net>
...hdog-Document-armada-37xx-wdt-bindin.patch | 52 +
...tchdog-add-documentation-for-armada-.patch | 37 +
...l-armada-37xx-add-nodes-to-support-w.patch | 44 +
...drvark-warm-reset-the-cores-and-card.patch | 115 +++
...drvark-warm-reset-the-cores-and-card.patch | 90 ++
...-marvell-Add-DTS-file-for-Turris-Mox.patch | 905 ++++++++++++++++++
...-cpufreq-armada-37xx-Fix-clock-leak.patch} | 0
126 files changed, 13461 insertions(+), 372 deletions(-)
126 files changed, 13436 insertions(+), 372 deletions(-)
delete mode 100644 target/linux/mvebu/patches-4.14/450-reprobe_sfp_phy.patch
create mode 100644 target/linux/mvebu/patches-4.14/90001-crypto-inside-secure-remove-null-check-before-kfree.patch
create mode 100644 target/linux/mvebu/patches-4.14/90002-crypto-inside-secure-do-not-use-areq-result-for-part.patch
......@@ -14937,10 +14937,10 @@ index 0000000..acbba76
+
diff --git a/target/linux/mvebu/patches-4.14/90121-PCI-aadrvark-warm-reset-the-cores-and-card.patch b/target/linux/mvebu/patches-4.14/90121-PCI-aadrvark-warm-reset-the-cores-and-card.patch
new file mode 100644
index 0000000..99712bc
index 0000000..09391ea
--- /dev/null
+++ b/target/linux/mvebu/patches-4.14/90121-PCI-aadrvark-warm-reset-the-cores-and-card.patch
@@ -0,0 +1,115 @@
@@ -0,0 +1,90 @@
+From 4039bc6263e4306bc8ceac6e2a381ec41d9f2221 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz>
+Date: Wed, 24 Oct 2018 16:55:11 +0200
......@@ -14957,10 +14957,10 @@ index 0000000..99712bc
+ drivers/pci/host/pci-aardvark.c | 46 +++++++++++++++++++++++++++++++--
+ 1 file changed, 44 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
+index 50e8addc22f9..5610fcb3f426 100644
+--- a/drivers/pci/host/pci-aardvark.c
++++ b/drivers/pci/host/pci-aardvark.c
+Index: linux-4.14.78/drivers/pci/host/pci-aardvark.c
+===================================================================
+--- linux-4.14.78.orig/drivers/pci/host/pci-aardvark.c
++++ linux-4.14.78/drivers/pci/host/pci-aardvark.c
+@@ -21,6 +21,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/of_address.h>
......@@ -14979,51 +14979,29 @@ index 0000000..99712bc
+
+ /* PCIe Central Interrupts Registers */
+ #define CENTRAL_INT_BASE_ADDR 0x1b000
+@@ -270,8 +274,25 @@ static void advk_pcie_set_ob_win(struct advk_pcie *pcie,
+@@ -270,6 +274,21 @@ static void advk_pcie_set_ob_win(struct
+ advk_writel(pcie, match_ls | BIT(0), OB_WIN_MATCH_LS(win_num));
+ }
+
++static void advk_pcie_warm_reset(struct advk_pcie *pcie)
++{
++ u32 reg;
++ u32 reg;
++
++ reg = advk_readl(pcie, CTRL_WARM_RESET_REG);
++ reg |= CTRL_PCIE_CORE_WARM_RESET | CTRL_PHY_CORE_WARM_RESET;
++ advk_writel(pcie, reg, CTRL_WARM_RESET_REG);
++ reg = advk_readl(pcie, CTRL_WARM_RESET_REG);
++ reg |= CTRL_PCIE_CORE_WARM_RESET | CTRL_PHY_CORE_WARM_RESET;
++ advk_writel(pcie, reg, CTRL_WARM_RESET_REG);
++
++ mdelay(100);
++ mdelay(100);
++
++ reg = advk_readl(pcie, CTRL_WARM_RESET_REG);
++ reg &= ~(CTRL_PCIE_CORE_WARM_RESET | CTRL_PHY_CORE_WARM_RESET);
++ advk_writel(pcie, reg, CTRL_WARM_RESET_REG);
++ reg = advk_readl(pcie, CTRL_WARM_RESET_REG);
++ reg &= ~(CTRL_PCIE_CORE_WARM_RESET | CTRL_PHY_CORE_WARM_RESET);
++ advk_writel(pcie, reg, CTRL_WARM_RESET_REG);
++}
++
+ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
+ {
++ struct device *dev = &pcie->pdev->dev;
++ struct device_node *node = dev->of_node;
+ u32 reg;
+ int i;
+
+@@ -311,10 +332,15 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
+ PCIE_CORE_CTRL2_TD_ENABLE;
+ advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
+
+- /* Set GEN2 */
++ /* Set GEN */
+ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
+ reg &= ~PCIE_GEN_SEL_MSK;
+- reg |= SPEED_GEN_2;
++ if (of_pci_get_max_link_speed(node) == 1)
++ reg |= SPEED_GEN_1;
++ if (of_pci_get_max_link_speed(node) == 3)
++ reg |= SPEED_GEN_3;
++ else
++ reg |= SPEED_GEN_2;
+ advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+
+ /* Set lane X1 */
+@@ -948,6 +974,8 @@ static int advk_pcie_probe(struct platform_device *pdev)
+ struct device *dev = &pcie->pdev->dev;
+@@ -955,6 +974,8 @@ static int advk_pcie_probe(struct platfo
+ struct pci_bus *bus, *child;
+ struct pci_host_bridge *bridge;
+ int ret, irq;
......@@ -15032,7 +15010,7 @@ index 0000000..99712bc
+
+ bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie));
+ if (!bridge)
+@@ -970,6 +998,20 @@ static int advk_pcie_probe(struct platform_device *pdev)
+@@ -977,6 +998,20 @@ static int advk_pcie_probe(struct platfo
+ return ret;
+ }
+
......@@ -15053,12 +15031,9 @@ index 0000000..99712bc
+ ret = advk_pcie_parse_request_of_pci_ranges(pcie);
+ if (ret) {
+ dev_err(dev, "Failed to parse resources\n");
+--
+2.19.1
+
diff --git a/target/linux/mvebu/patches-4.14/90122-ARM64-dts-marvell-Add-DTS-file-for-Turris-Mox.patch b/target/linux/mvebu/patches-4.14/90122-ARM64-dts-marvell-Add-DTS-file-for-Turris-Mox.patch
new file mode 100644
index 0000000..47a146e
index 0000000..d4b7df0
--- /dev/null
+++ b/target/linux/mvebu/patches-4.14/90122-ARM64-dts-marvell-Add-DTS-file-for-Turris-Mox.patch
@@ -0,0 +1,905 @@
......
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